`include "../include/cpu_defines.sv"
module RAT(
	input logic cpu_clk,
	input logic cpu_rst_n,
	input logic [5: 0] search1,
	input logic [5: 0] search2,
	input logic [5: 0] search3,
	input logic [5: 0] search4,
	// input logic [5: 0] search5,
	// input logic [5: 0] search6,
	input logic en1,
	input logic en2,
	input logic [5: 0] daddr1,
	input logic [5: 0] daddr2,
	input logic [5: 0] din1,
	input logic [5: 0] din2,
	input logic flush_en,
	input logic [`REG_NUM-1: 0][5: 0] flush,
	output logic [5: 0] out1,
	output logic [5: 0] out2,
	output logic [5: 0] out3,
	output logic [5: 0] out4
	// output logic [5: 0] out5
	// output logic [5: 0] out6
);
	// physic reg : 64
	(* RAM_STYLE="distributed" *)
	logic [5: 0]  rat[`REG_NUM-1: 0];

	assign out1 = rat[search1];
	assign out2 = rat[search2];
	assign out3 = rat[search3];
	assign out4 = rat[search4];
	// assign out5 = rat[31];
	// assign out6 = rat[daddr2];
	// assign out5 = rat[search5];
	// assign out6 = rat[search6];

	always_ff @(posedge cpu_clk)begin
		if(cpu_rst_n == 1'b0)begin
			for(int i=0; i<`REG_NUM; i++)begin
				rat[i] <= i;
			end
		end
		else if(flush_en)begin
			for(int i=0; i<`REG_NUM; i++)begin
				rat[i] <= flush[i];
			end
		end
		else begin
			if(en1)begin
				rat[daddr1] <= din1;
			end
			if(en2)begin
				rat[daddr2] <= din2;
			end
		end
	end
endmodule

module RatCheckPoint(
	input logic cpu_clk,
	input logic cpu_rst_n,
	input logic [5: 0] search1,
	input logic [5: 0] search2,
	input logic [5: 0] search3,
	input logic [5: 0] search4,
	input logic en1,
	input logic en2,
	input logic en3,
	input logic en4,
	input logic [5: 0] daddr1,
	input logic [5: 0] daddr2,
	input logic [5: 0] daddr3,
	input logic [5: 0] daddr4,
	input logic flush,
	output logic out1,
	output logic out2,
	output logic out3,
	output logic out4
);

	logic [`REG_NUM-1: 0] rat;
	assign out1 = rat[search1];
	assign out2 = rat[search2];
	assign out3 = rat[search3];
	assign out4 = rat[search4];


	always_ff @(posedge cpu_clk)begin
		if(cpu_rst_n == 1'b0 || flush)begin
			rat <= 34'h3ffffffff;
		end
		else begin
			if(en1)begin
				rat[daddr1] <= 0;
			end
			if(en2)begin
				rat[daddr2] <= 0;
			end
			if(en3)begin
				rat[daddr3] <= 1;
			end
			if(en4)begin
				rat[daddr4] <= 1;
			end
		end
	end

endmodule